The AN-H61 design uses a self-oscillating, second-order, sigma-delta modulator circuit to convert a small analog audio input signal into two, 200 to 800KHz complementary PWM logic signals. There are two diode-capacitor bootstraps to power the high-side MOSFET gate drives. The low-side gate drives are powered directly by the VDD2 voltage.
The logic and internal voltage reference circuits are powered by the AVDD voltage supply. The VDD1 is the internal level translator power supply. AVDD and VDD1 are connected to the same voltage as the VDD2. This voltage rail on the
demoboard is called VNF and is referenced to VNN. It should be between 9 - 12V. The voltage should be selected according to the size of the power MOSFETs, gate threshold, and PWM frequency of the class-D amplifier.
